NXP Semiconductors /LPC18xx /MCPWM /INTEN_CLR

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Interpret as INTEN_CLR

Description

Interrupt Enable clear address

Fields

ILIM0_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
IMAT0_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
ICAP0_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
RESERVED	Reserved.
ILIM1_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
IMAT1_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
ICAP1_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
RESERVED	Reserved.
ILIM2_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
IMAT2_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
ICAP2_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
RESERVED	Reserved.
ABORT_CLR	Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
RESERVED	Reserved.

Links

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